The present invention relates to a data transfer control device and electronic equipment, and, in particular, to a data transfer control device and electronic equipment for performing data transfer that is based on a standard such as IEEE 1394 between a plurality of nodes that are connected by a bus.
An interface standard called IEEE 1394 has recently been attracting much attention. This IEEE 1394 lays down standards for high-speed serial bus interfaces that can handle the next generation of multimedia devices. IEEE 1394 makes it possible to handle data that is required to have real-time capabilities, such as moving images. A bus in accordance with IEEE 1394 can be connected not only to peripheral equipment for computers, such as printers, scanners, CD-RW drives, and hard disk drives, but also to domestic appliances such as video cameras, VTRs, and TVs. This standard is therefore expected to enable a dramatic acceleration of the digitalization of electronic equipment.
However, it has become clear that there are some technical problems that can occur in a data transfer control device in accordance with IEEE 1394, as described below.
That is to say, the current IEEE 1394 standard does make it possible to implement transfer speeds up to a maximum of 400 Mbps. In practice, however, the presence of processing overheads forces the actual transfer speeds of the entire system to be much slower. In other words, the firmware and application software running on a CPU require large amounts of time for processes such as preparing to receive data and fetching the receive data, which means it is not possible to implement high-speed data transfer overall, no matter how fast the data can be transferred over the buses.
A particular problem lies in the fact that a CPU incorporated into peripheral equipment has a lower processing capability than the CPU incorporated into the host system, such as a personal computer. This makes the problem of processing overheads in the firmware and application software extremely serious. It is therefore desirable to provide techniques that are capable of efficiently solving this overhead problem.
The present invention was devised in the light of the above described problems and has as an objective thereof the provision of a data transfer control device that makes it possible to reduce processing overheads in firmware or the like and implement high-speed data transfer with a compact hardware configuration, and electronic equipment using the same.
In order to solve the above described problems, a data transfer control device of the present invention for performing data transfer in accordance with the IEEE 1394 standard between a plurality of nodes connected to abus comprises: a link circuit that provides a service for packet transfer between the nodes; and a write circuit that writes a packet, which has been received through the link circuit, to a packet storage means which is randomly accessible, wherein the link circuit performs processing to check a header CRC or a transaction code included within a header of the packet received from another node and, performs processing to invalidate the packet when it is determined that there is a CRC error in the header of the packet or when it is determined that the transaction code of the packet is an unknown code.
This aspect of the present invention makes it possible for the link circuit to perform processing to invalidate (i.e., cancel) a packet when there is a CRC error in the header of that packet or when the transaction code of the packet is unknown. This makes it unnecessary for the firmware to perform any processing on that packet. As a result, processing load on the firmware can be reduced, enabling an increase in the data transfer speed.
When it is determined that there is a CRC error in the header of the packet, the packet may be invalidated by returning a header pointer indicating a received header position within a header area of the packet storage means, to a position indicated by the header pointer at a completion of a previous packet reception. This makes it possible to invalidate the packet by the simple process of returning the header pointer, even if a first part of the header has already been written to the packet storage means.
The data transfer control device may further comprise means for storing status information indicating that the header CRC brror has occurred. The data transfer control device may further comprise means for storing status information indicating that the packet with an unknown code has been received. This makes it possible to inform the firmware of statuses, when the firmware should need to know that a header CRC error has occurred or that a packet with an unknown code has been received.
When it is determined that the transaction code of the packet is an unknown code, the packet may be invalidated by ensuring that the packet is not written to the packet storage means. This makes it possible to reduce the processing load on the firmware by not saving that packet.
No reception completed status may be generated when it is determined that there is the CRC error in the header of the packet or when it is determined that the transaction code of the packet is an unknown code. This makes it unnecessary for the firmware to perform interrupt processing, preventing wasteful processing of the firmware.
A data transfer control device of the present invention for performing data transfer in accordance with the IEEE 1394 standard between a plurality of nodes connected to a bus comprises: a link circuit that provides a service for packet transfer between the nodes; and a write circuit that writes a packet, which has been received through the link circuit, to a packet storage means which is randomly accessible, wherein the link circuit performs processing to check a data CRC included within data of the packet received from another node and, performs processing to validate the header of the packet and invalidate the data of the packet when it is determined that there is a CRC error in the data of the packet.
This aspect of the present invention makes it possible for the link circuit to perform processing when a data CRC error occurs, such that the header of that packet is validated but the data alone is invalidated. This makes it unnecessary to perform processing to read that data, reducing the processing load on the firmware. This configuration by which the header is not invalidated but is left as is ensures that the firmware can perform suitable processing for when a data CRC error occurs.
When it is determined that there is the CRC error in data of the packet, the data may be invalidated by returning a data pointer indicating a received data position within a data area of the packet storage means, to a position indicated by the data pointer at a completion of a previous packet reception, without returning a header pointer indicating a received header position within a header area of the packet storage means. This makes it possible to invalidate a packet by the simple process of returning the data pointer.
A data transfer control device of the present invention for performing data transfer in accordance with the IEEE 1394 standard between a plurality of nodes connected to a bus comprises: a link circuit that provides a service for packet transfer between the nodes; a write circuit that writes a packet, which has been received through the link circuit, to a packet storage means which is randomly accessible; and means which sets a first mode, in which a received broadcast packet is invalidated, and a second mode, in which the received broadcast packet is validated, wherein the link circuit performs processing to check a destination ID included in a header of the packet received from another node and, performs processing to invalidate the packet when it is determined that the packet is the broadcast packet and the first mode has been set.
This aspect of the present invention makes it possible to select operation in either a first mode in which received broadcast packets are invalidated or a second mode in which they are validated, further increasing the universality of the data transfer control device. If a broadcast packet is received when the first mode has been set, the link circuit performs processing to invalidate that packet. This makes it possible to avoid wasteful processing and to increase the data transfer speed.
When it is determined that the packet is the broadcast packet and the first mode has been set, the packet may be invalidated by not writing the packet to the packet storage means. This makes it possible to avoid wasteful processing by not performing processing to write to the packet storage means.
Electronic equipment according to the present invention comprises any one of the above described data transfer control devices; a device which performs given processing on data that has been received from another node through the data transfer control device and a bus; and a device for outputting or storing data that has been subjected to processing. And, a device which performs given processing on data that is to be transferred to another node through the data transfer control device and a bus; and a device which takes in data to be subjected to processing.
These aspects of the present invention make it possible to increase the speeds of processing within the electronic equipment for outputting or storing data that has been transferred from another node, or of processing within the electronic equipment for transferring data, which was taken in to the electronic equipment, to another node. Since these aspects of the present invention also make it possible to reduce the size of the data transfer control device and also reduce the processing load on the firmware or the like, electronic equipment can be made less expensive and more compact.